Ziptronix was founded in September 2000 as a spin-out from the Research Triangle Institute (www.rti.org) “to commercialize ten years of research and development leading to the fabrication of three-dimensional ICs.” The company has raised $6.5 million in first-round financing, led by Alliance Technology Ventures and including Xilinx. The company has 18 employees.

Ziptronix claims to be the only company able to provide room temperature, non-adhesive wafer-to-wafer and die-to-wafer bonding and interconnect for a wide variety of semiconductor materials. Ziptronix is commercializing a process that achieves permanent, covalent bonding of semiconductor materials at room temperature without adhesives. For those of you that have forgotten your high-school chemistry, a covalent bond is formed when two molecules share electrons. The ZiROC process ensures a uniform covalent bond across the wafer interface and has been independently certified to exceed MIL-STD-883E hermetic leakage specifications.

Two proprietary Ziptronix technologies form the basis of its process: room temperature wafer bonding and backside processing.

Adhesive-less room temperature bonding eliminates stresses created by the distinct thermal coefficients of expansion of different materials. Thermal fusion, anodic, glass-frit and other conventional wafer bonding methods employ high temperatures, electric fields or materials that are foreign to the fab environment. The Ziptronix process removes costly processing steps associated with less effective adhesive/thermal/ pressure-based bonding techniques and precludes the introduction of exotic adhesive chemistry into high volume fabs. Ziptronix’ process uses only standard fab equipment, chemicals, and protocols and scales seamlessly to 300 mm.

Bonding forces greater than the fracture threshold of the individual materials are realized, ensuring the resulting 3-D structure remains intact. As a result, aggressive thinning via back grinding, lapping and/or Chemical Mechanical Polishing (CMP) can be performed without fear of material separation at the bond interface. Layers can be thinned to less than ten microns, exposing the ‘backside’ of the thinned layer, for further processing.

The bonding technique’s two-step sequence readily accommodates the fab cycle of queuing and production. Surface activation (Step 1) can precede bonding (Step 2) by several hours without deterioration of the activated surfaces. Then, when active surfaces are bonded, the process occurs on contact without applied pressure or an electric field, facilitating high production throughput. Bonding activation is typically dual-sided, but can be confined to a single side.

Ziptronix’s 3-D circuit process consists of the following steps:

• Wafer or die surfaces are activated using standard fabrication chemical processes

• Wafer or die are aligned — within 1u for high density interconnect

• Covalent bonds are created at room temperature without adhesives

• A layer is thinned (to within 5u) exposing the backside of its active components

• Standard via and metalization techniques are applied to interconnect layers

• Resulting 3D structure is placed in standard packages

The Ziptronix process starts with a host wafer. Then, other wafers or individual chips are bonded to the host at room temperature. The substrate from the second wafer or individual chips is then thinned, leaving only a few microns containing the active electronics. Electrical interconnects are then made between the host and the bonded wafer or die using a standard via-based interconnect process identical to that used in semiconductor fabs. The process can be repeated multiple times, resulting in the integration of many chips into a single 3D structure.

The ZiROC technology allows aligned wafer-to-wafer and die-to-wafer bonding using standard process equipment, in ambient fab conditions. Combined with Ziptronix’ post-bonding backside processing and interconnect process, the technology enables the 3D integration of existing devices and, ultimately, the fabrication of custom solid-state systems architected in three-dimensions.

High accuracy wafer, die and device level alignment (within 1 micron) between layers can be achieved, facilitating high density interconnect between layered devices. Once aligned, bonded and thinned, standard fabrication techniques are employed to interconnect layers. Accessing circuits from the backside, the Ziptronix process uses vias “drilled” through layers to access landing pads in lower layers with standard metalization techniques used to form the final circuit structure, which is no thicker than a standard 2D circuit thanks to the thinning process.

Ziptronix claims that this process will facilitate the creation of individual 3-D transistors with significantly reduced parasitic capacitance, lower operating voltage and power consumption, and higher operating frequencies and current densities than their 2-D counter parts. Ziptronix has created a Symmetric Intrinsic Hetro-junction Bipolar Transistor (SIHBT) that operates at 100GHz using these bonding and alignment techniques.

In summary, with this process, Ziptronix introduces four key initiatives:

• Existing fab utilization

• Adhesive-less room temperature bonding and thinning

• High precision alignment

• 3D or dual-sided device-level interconnect structures

Ziptronix plans to license the technology to large semiconductor firms, to produce integrated parts for electronic firms, and eventually to produce standard parts employing the technology. Initially the company will co-develop parts for large semiconductor firms. Ziptronix has an in-house prototyping fab for wafer bonding, wafer-scale encapsulation and the production of 3D ICs. A brief, optimized process flow allows the bonding to be achieved at a cost lower than traditional methods. Ziptronix projects costs of less than $200 per wafer pair, in production quantities.

Key markets and applications include wafer scale encapsulation for RF/SAW filters and MEMS devices, engineered substrates for RF/SAW filters, and 3DICs (12-24 months). While 3D devices sound exciting, initial target applications are more modest and include custom engineered substrates for temperature compensation and other thermal management needs and wafer-scale, hermetic encapsulation of MEMS and other surface-sensitive devices.

Using its process, Ziptronix can fabricates exotic substrates such as InP on silicon with a thin oxide layer separating the materials. Hermetic encapsulation keeps surface sensitive devices like MEMS in the foundry until they are sealed, and eliminates the need for expensive, ceramic packages. Temperature compensating substrates can be bonded to a piezoelectric substrate to enhanced RF performance and lower cost. For optical MEMS applications, a simple 3 piece assembly can replace, at wafer scale, a complex, eutectic & epoxy semi-hermetic approach, increasing yields and lowering cost.

Ziptronix expects to generate revenue by year-end and has engaged with one of the largest producers of MEMS devices.

Doug Milner, Chairman, President and CEO (former president of Invensys Energy Systems)

Robert (Bob) Markunas, VP of Marketing (previously a technical leader and director of the Center for Semiconductor Research at RTI)

Dr. Paul Enquist, VP of R&D (previously developed the symmetric processing technology while working on research in achieving high-performance electronics using heterogeneous bipolar transistors (HBT) at RTI)