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Calypto Design Systems -- Sequential Logic Equivalence Checking Tool
Founded: Jan 2003
Status: Private
Issue(s): 5/03, 9/05
2933 Bunker Hill Lane, Suite 202
Santa Clara, CA 95054
Tel: 408/850-2300
Fax: 408/850-2301

Calypto Design Systems was founded in 2002 “to bridge the gap between Electronic system level design and IC implementation.” Calypto has raised more than $22 million in Series A and Series B funding from Tallwood Venture Capital, Walden International, JAFCO Ventures, and Cipio Partners (Infineon Ventures). The company has 51 employees.

Calypto intends to broadly deploy EDA products that will connect system-level models and RTL design flows in order to support faster verification times and design at a higher level of sequential abstraction. According to Calypto, designers require three technologies to successfully navigate the System-level-RTL continuum: System Level Equivalency Analysis, RTL-System Level Reverse Synthesis, and System-level Synthesis and prototyping. Calypto will develop or partner to ensure that all three technologies, as well as supporting methodologies, are commercially available and viable for use by design teams.

Functional verification is consuming up to 75% of total design time and resources, yet, an estimated 45% of all design starts require multi-million dollar silicon re-spins because of undetected functional bugs. The fastest way to find functional errors and verify system requirements is to design and verify at a higher level of abstraction.

There are two different directions in which designers are moving up in abstraction: sequential abstraction, and data abstraction. Data abstraction is simply going from managing “bits” to managing “words” or even complete data structures. Sequential abstraction is where a design moves up from a fully scheduled, timed implementation to an un-timed or fully algorithmic description.

Calypto’s SLEC product family is claimed to be the only sequential logic equivalence checking solution, offering dramatic improvement in IC functional verification. With SLEC, design teams can improve verification effectiveness across the entire System-to-RTL continuum – from transaction-level models to fully-timed RTL implementations. The SLEC sequential equivalence checking software is based on a patent-pending hybrid verification technology that, unlike traditional combinational equivalence checkers, can support designs with sequential differences.

Micro-architectural refinements (such as retiming, pipelining, state re-encoding and resource sharing) change the sequential nature of designs, and thereby move up in a sequential level of abstraction from a pure RTL level. However, these changes have not been well-supported by a standard EDA design flow.

The SLEC product family proves functional equivalence between two IC designs that contain differences in levels of abstraction and sequential behavior. SLEC can verify designs with sequential differences such as micro-architectural changes, state machine modifications, timing re-balancing, and interface differences. The product family initially includes two products: SLEC SYSTEM and SLEC RTL.

SLEC SYSTEM verifies that RTL implementations match hardware intent captured in system-level models written in SystemC and C++. Unlike simulation testbenches, SLEC SYSTEM verifies functionality in spite of design differences in throughput, latency and I/O.

SLEC RTL checks functional equivalence between two versions of an RTL design that have dramatically different architectures and timing. It can be used to verify that RTL optimizations for power, timing and area do not introduce functional defects.

Calypto is collaborating with Mentor to integrate the Calypto SLEC sequential equivalence checker with Mentor’s Catapult C Synthesis tool, providing IC designers with a joint, verifiable, automated flow from an algorithmic chip description to an RTL description. The company has working relationship with other high level synthesis companies and is also a member of Connections, OpenDoor, Synopsys SystemVerilog Catalyst, Virage, and Novas’ Harmony programs.

The SLEC product family is available with support for Verilog, VHDL, SystemC and C/C++ hardware descriptions. Pricing for SLEC products begin at $175,000 for a one year floating license on Linux platforms. Customers include Renesas and the Freescale PowerPC core development team.

Devadas Varma, Ph.D., CEO, President and Co-Founder (previously founder and Managing Director of Caltos Capital, CTO of Ambit Design Systems, a Cadence Fellow and VP and CTO of the Ambit Group of Cadence, following the acquisition of Ambit)

Gagan Hasteer, Ph.D., VP of Engineering and Co-Founder (previously Director of Engineering at Innologic Systems, a start-up in the formal verification arena, and an early member of the Ambit engineering team)

Larry Lapides, VP of Sales (previously spent the last 6+ years at Verisity Design, holding executive positions in business operations, marketing and worldwide sales including VP of worldwide sales)

Anmol Mathur, Ph.D., Chief Architect and Co-Founder (previously the architect of the datapath synthesis and optimization group at Ambit and Cadence)

Sanjiv Narayan, Ph.D., VP & Managing Director, Calypto India (previously a senior architect at Cadence and worked at Ambit and Viewlogic)

Michael Sanie, VP of Marketing and Business Development (previously group director of strategic industry initiatives at Cadence and director of marketing and business development for IC design at Numerical Technologies)

Eiki Suzuki, President, Calypto, K.K. (previously executive advisor, leading the Japanese business for Cadence and Get2Chip and founder, CEO and executive advisor for SC Hightech and Sumisho Electron Devices)

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